I am not sure about a "similar result".
Hmm... After looking once again finally I had spotted what is the crucial difference in our simulations. Mine includes rudimentary the additional pulse length correction (remember, it can be sensed only rising up from 0V). It is "rudamentary" as it adds fixed 1µs to hardware time, which allows my MC simulation predictably with physical observations to arrive to similar count rates at high count rate (I am talking about >1M of count rates, and >800nA currents).
Ok, what I am babbling here? Maybe some illustrations will clear things up.
it is pulse sensing which miss the pulses and mess up the measurements. The detector, pre-amplifier and shapping amplifier forwards all information to gain and pulse sensing and PHA electronics (basically detector itself produce no dead time). Yes shapping amplifier tends to convolute the information a bit (albeit no information loss is there, and it can be deconvoluted with right signal processing techniques), and that troubles the oversimplified pulse sensing circuit from correctly recognizing every pulse with increasing pulse density.
So at least on Cameca hardware Gain electronics reverse the signal (pulses are negative). There are different designs of using Sample/Hold together with comparator for pulse sensing, and it looks that Cameca used the worst possible way (I see some reason behind why they do that way - they kinda shoot two foxes here with single bullet: this do pulse sensing and get rid from detecting noise as a pulse... but when if there are lots of "foxes" this shooting blows hunters own foot-off...
). There is 3 elements which work together to sense a pulse: comparator (compares two analog signals), sample-and-hold chip (which have two modes, in first mode it passes a bit delayed analog signal (from gain-amplified signal as an input), second mode is triggered when S/H pin is set HIGH – it takes a sample (which takes some short time) and hold (and output it) so long as S/H pin is kept HIGH. And the third element on Cameca design is a D-flip-flop. It is the component which glues the feedback of comparator, FPGA or microcontroler and sample and hold chip. Comparators output goes as Clock input of D-flip-flop chip.
This kind of D-Flip-flop reacts only to the rising edge of comparators output (As a clock input, it ignores falling edge). Additional constraint is that it reacts to such rising edge only if its state is cleared - that is when flip-flops CLR pin is triggered and D is set to HIGH. The Clock rising edge of flip-flop then triggers (sets HIGH) its output Q which forwards that state to two devices: to FPGA (where it increases counter for integral mode counting by one); and other copy of Q state goes to Sample/Hold chip where it triggers and holds the S/H pin HIGH, so that S/H chip stops tracking the input but starts sampling and holding the amplitude of the pulse. The FPGA for set hardware time pulls the CLR and D to LOW and thus Flip-Flop is made inactive and does not react to any further CLK input from comparator. It does that for selectable amount of hardware enforced dead time (where on Cameca it is integer number of µs). The comparator compares the Gain-amplified and reversed signal (the main input to this pulse sensing circuit) and the output of Sample-and-hold chip (which takes gained reversed signal and reverses it one more time thus its output is uptight), the comparator output is set to HIGH if output of S/H chip is higher than main input of reversed gained signal (some of Comparators can have some threshold value for difference to switch the output state).
So below illustrations show these events in some unit-less time line. It contains two parallel time axes showing on top two analog inputs of the comparator, and below is shown the digital (TTL) output of comparator corresponding to the relation between those two analog inputs. At first lets look to the worst case scenario:
dashed blue line here marks how signal would look if S/H would be not pulled HIGH. TTL logic depends from generation of electronics. In old times it was 5V (TTL), newer designs moved to (LV)TTL - that is 3.3V.
The crucial thing is that FPGA will unblock the flip-flop after set enforced hardware dead time times out, but in some cases the comparator is still kept at HIGH state and thus prolonging the effective blocking of the sensing any new pulses, and thus it makes additional hardware dead time which depends from 2 things: First, the pulse length at positive side (at 0V, not at half amplitude) and in case of Cameca pulses it is about 1µs. In presented above worst case scenario that is about additional 1µs. Second, The probability of such pulse to appear at such position overlapping with the - that depends from count rate.
The best case scenario is that there is no other pulse too-close to enforced dead time lifting moment and the comparator can be put to LOW state with very small delay after hardware enforced dead time is lifted. I emphasize the "small delay" - that will be not 0, and will depend from two factors: 1) the amplitude it was holding (the higher amplitude it was holding the longer way down to 0V, the delay will be bigger); 2) how fast the output can restore to track the input after the S/H pin is lowered. So, Indeed, this delay will depend from GAIN and HV BIAS but as it will be small, and its effects can statistically interfere only some range of counting rates, there never was straight forward linkage found.
The best case scenario:
And then at medium count rates there will be lots of intermediate situations:
there as we see the pulse which prolong the dead time happened at enforced time, its long pulse time however goes over that enforced time and prolongs the dead time after.
As this can be seen in the above pictures, this additional dead time will depend from pulse density and length of pulse. Would be the S/H chip comparator and flip-flop connected in better way the time span of pulse would have no influence to the result.
So my initial model adds +1µs to the dead time, and comes at observable count rate at very high count rates (>1Mcps), probably (I need to check) it is underestimating the observable counts at mid-range. I am rewriting that part to address that.
edit: Just to correct my claim about 1µs, actually pulse length measured at 0V is not 1µs but 1.2µs.
