I'm guessing that they squeeze the PHA signal into 0 to 5 volts and 8 bits because they are only using an 8 bit MCA (multi channel analyzer) to perform the PHA integration? That is the returned PHA intensity data is always 0 to 255 integers.
I really like this MCA PHA feature on the Cameca as it is much faster than the SCA (single channel analyzer) serial method used by JEOL. I just wish they used a better MCA, say 16 bit...
MCA is just a buzz word. Seriously. It some kind of bookish abstraction, as raw pulses are still analyzed sequentially (serial). (Fun fact: Even EDS is serial/sequentially analysed, it just happens so fast that it looks it updates many channels at once). The question would be why that SCA on Jeol works slower (maybe it is more precise? probably it lets the signal in the pipeline to reset to zero before processing next pulse, where on Cameca it is rushed). What is max throughtput with SCA on JEOL? Cameca WDS throughtput ceiling is about 300kcps (at PHA integral mode with 1µs dead time set). So there actually is nothing like 8 bit MCA on Cameca, as MCA is abstraction of bunch of components designed to work like one, and not some off-shelf ready-to-use component (albeit You can buy such devices, but Cameca "MCA" is custom designed and programmed). The main parts of MCA on Cameca is pulse hold chip (as amplified pulse needs to wait in line for multi spectrometer shared ADC (analog-digital conventer) to be freed), then muxer (many-into-one), then ADC, and then micro-controller/processor (older use two philips 680xx, new use single FPGA which includes all MCA logic and VME communication protocoles in single package). So "MCA" is just a bunch of components coupled with custom written logic. Now when it comes to Phillips 68070 - it is 16bit/32bit microprocessor. The only bottleneck is 8bit ADC. FPGA are actually bit-agnostic (as logic is customely written, the implementation decides about bus width it can be even bizarre bit number like 22bit). I guess that ADC it is limited to 7 from 8bit in old design as (1) there were not enough input pins to Phillips 68070, probably that is the same reason why a single ADC serves 3 spectrometers. Three independently connected 8bit ADC would need 8*3 pins + clock/read_enable * 3 which would be 27 i/o pins (+ 3 for pulse hold), where implemented muxed design needs only 7 pin + 3 spectrometer selection pins (in sum 10 pins + 3 pulse hold). There are 2 68070 on old board. If took a close look to the board it is obvious that it is already fully crowded and there is no place for 3rd 68070. Also there comes ADC delay, generally the more wider the bus the more clock cycles needs to pass for outcome to be output after input. It normally cause no trouble in sequentially digitized single pulse source, but because this is muxed (full word for that is "multiplexed" btw), it would over-complicate design tremendously. And so limitation to 8bit ADC in old design has its reasons.
But when I look to new design (with FPGA) I see completely no possible limitations which would still force using 8bit ADC and muxing the pulses to single ADC. The board was downsized, that large free space is effect of merging MCU and VME logic into a single FPGA. There is no space constraints. I guess that used FPGA probably has enough pins (and even if it is not, just use a bit more beefy FPGA, some commercially available FPGAs expose thousands of i/o pins), I can't understand the reason that muxing of pulse signals is still here, probably it is just saving a some $, can't explain it otherwise. The 12bit ADC got pretty fast and cheap in last decades, there are plenty good candidates. (most of EDS MCA use 12bit, as that is still very fast, and gives 4096 channels which is plenty enought).
But before moving to even up to 12bits, the amplification part needs to be revised, as it clearly adds lots of statistic noise (broadens tremendously the PHA peak) and that looks just ctrl-c, ctrl-v from previous design.
I already wrote that some time ago, but will repeat myself: How is that possible that on oscilloscope (cheapo, slow Chinese no name brand worth 250$) hanged to signal coming from pre-amplifier circuit clearly exposes amplitudes of single and double pile ups with piled up Ar escape pulses, but at PHA graph it is just single muddled peak? The only explanation I can come up is that gain amplification introduce lots of statistic noise and pulse hold chip is not registering maximum amplitude. Signal is worsened a lot somewhere between charge pre-amplifier and ADC.
So In my opinion it would be best to move away from centralized processing, and distribute small FPGAs per spectrometer with 12 bit ADC directly digitising the signal outputted from charge pre-amplifier circuit and feeding to small FPGA. No more muxing, no peak holding, no cascade OPAMP amplification, impedence mismatching due to different frequency (pulse density) response, sending of analog signals for kilometers (exagerated, but even those few meters has its impact)... I even am not sure that this would be expensive.
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