WDS preamplifier design

[Brian Joy]

OK, then are you saying that the Cameca instrument performs an extra step of converting from mono-polar to bipolar pulses, that the JEOL electronics does not?  And that is the reason for the thinner PHA peaks on the Cameca pulse processing electronics?

Sorry if I ask dumb questions, I am not familiar at all with these electronic details.

Those are not dumb questions, those are actually very valid questions, just  a bit in this context inpatient like "a-cart-attached-before-the-horse". The answer is, unless someone would invite me to peek into Jeol Probe electronics (at least to detector electronics), it is hard to tell.

So if we open the case where the Shapping of pulse takes place we see this (My kind reminder: DEADLY high voltage is present on part of such board):

The Charge-Sensitive Preamplifier (CSP) and the Shapping Amplifier (SA) are packed inside single a single chip produced by Amptek - A203. The SA on that chip offers both: bipolar (pin9) and unipolar (pin8) outputs, however from visual inspection it is clear that Cameca uses unipolar (pin8, a clear trace from it, then around A203 to the capacitor for decoupling, which is required by documentation of A203) output from that chip and by components placed on the shielded ground plane (which points to very careful design for sensitive signal handling) it is clear that it does the 2nd differentiation on its own implementation (with OPAMP AD847). But why? I believe it is as A203 is not able to drive terminated (75ohm) coaxial cable on its own as A203 bipolar output is rated for 2kohm impedance - connecting such signal directly to terminated coaxial (75ohm) would lower down the amplitude a lot (x30 times), thus I think Cameca uses its own implementation with 2nd differentiation of monopolar pulses and (what I suspect from clearly visible two diodes and connection with NPN and PNP transistor pair) signal after that differentiation goes through class AB power amplifier (the short explanation what it is: https://www.elprocus.com/class-ab-amplifier/) as signal needs to be driven through few meter terminated coaxial cable to the gain and counting electronics. Just a side note: there are hardly any high speed OPAMPS which could directly drive such loads at these voltages (+/-15V), and thus the engineering of Cameca in this regard is a top notch.

So to answer the question if Jeol "shortcuts" on signal handling and thus PHA distribution suffers because of that - that would need similar inspection on Jeol hardware side: We need to know, what CPS and SA it uses (i.e. A203 is unique in its integration of both CSP and SA into single package - but it is possible to use separate CSP and SA chips (i.e. produced by Cremat inc.) to get the similar functionality), what kind of coaxial cable is used to send the signal from detector to counting board. Design for a few hundred of thousands of pulses a second is not complicated. However with Million pulses in second a single weak point in design can cause the amplitude drop.

This 75 ohm terminated coaxial cable is making me a headache for my planned experiment with external pulse generator. This means I will need to implement some fast class AB power amplifier if I want to simulate the pulses from the above presented circuit.

I however am skeptical if above described part of pipeline would produce observed differences in severity of PHA shift and broadness on Jeol probes. I introduced the description of bipolar pulse as a starting point to go further with explanation what happens next - when density of such pulses increase (count rate increase). We also can see the PHA shift on Cameca instruments and PHA distribution goes straight to hell when going to very high input count rates (like >1Mcps). And PHA shifting if using normal bias values is visible already from 20kcps and up.

So at first I want to present how I know the PHA shifts are produced on Cameca WDS hardware and in particular - how the bipolarity of pulses is causing that. Also my presented mitigation for "downsizing" (not to mistake with PHA shift) has a part in this story, and knowing if early shift can be mitigated by lowering the bias and increasing the gain can shed some light why Jeol PHA has more severe shifts (and broadening). I guess that there is not much difference of how Cameca converts unipolar to bipolar (doing math differentiation with OPAM), but how unipolar pulses looks like and differs by different handling of SA and CSP used by these two vendors. Unfortunately everything in pipeline before the bipolar pulse is more theoretical, as only bipolar output can be captured with oscilloscope. Nevertheless, knowing the process it is possible to reconstruct earlier shapes in the pipeline and find the possible reason even without opening the case and looking to the physical components of electronics.

I’ve attached datasheets for the Amptek A203 and also for the A250.  From the photo on the A203 (and 206) datasheet, it appears that the can contains a mini-circuit board with relatively few (surface-mount) components; it is likely a very simple circuit, but the datasheet provides only minimal information on its design.  Figure 8 from the datasheet for the presumably similar A250 provides a little more detail, but nothing is given on construction of the amplifier (still just an empty triangle).  I don't understand the need for the push-pull transistors at the output of the CAMECA circuit, as the AD847 should be able to drive the cable directly.

The JEOL WDS charge-sensitive preamplifier is constructed from discrete through-hole components (thank god); aside from capacitors, the component count is low.  The transistors used in the circuit are of the low-noise type typically used in high quality audio amplifiers; I’ve attached datasheets.  The circuit is shielded with copper plate and housed within a small steel box attached to the spectrometer.  In the photo below, the long wire with thick insulation that runs parallel to the length of the box is the high voltage supply for the X-ray counter, with exposed high voltage at the binding posts (TM1, TM2) in the upper left along with two large, light blue ceramic bypass capacitors.  The X-ray counter anode wire is in continuity with the heavily insulated terminal on the far left.  The additional light blue ceramic capacitor on the far left is the coupling capacitor, C3, that blocks the X-ray counter anode bias; thus, aside from TM1 and TM2, the entire circuit board operates somewhere within the range +/-15 V.  The red and white wires on the far-right are the respective +15 V and -15 V supplies, while the black wire is circuit common.  The single test point (TP1) is mostly hidden by the insulated high voltage wire and is just barely visible adjacent to resistor R11; it is located at the noninverting input of the buffering op amp (see below).  Variable resistor VR1 (see below) is located near the top margin of the board and has a yellow cross-slotted rotor within a square blue case.  The six bulbous, blue components toward the right are 10 μF Ta bypass capacitors.  A number of smaller, blue ceramic bypass capacitors are also visible, as are blue (metal film) color-coded resistors.  Capacitor C5 (see below) is the glossy dark brown component immediately adjacent to the R8 label.  The various transistors are all located in the lower middle of the circuit board and are housed in black plastic TO-92 cases.  The circuit is designed to operate at low power.



I’ve constructed a simulation of the circuit in LTSpice (free download!), with the schematic below generated from the software.  I had to change transistors to ones that were available in the database, and I’ve noted each substitution on the schematic.  My substitutes may serve reasonably well, but some resistor values likely need to be changed in order to bias the output more easily.  Also, I substituted the AD811 op amp for the AD817; this should have no effect on behavior of the circuit as drawn below.  For the sake of simplicity, I fed a 100 Hz sine function, V(t), into the input and arbitrarily assigned an amplitude of 1 mV (so V_peak-peak = 2 mV).  With some fiddling of VR1, I was able to get the output centered at 0 V.



The circuit constitutes a charge-sensitive (and inverting) preamplifier.  Variation in current at the input is inversely proportional to dV/dt at the output.  Capacitor C3 is a coupling capacitor that blocks the bias (DC) on the X-ray counter anode and also differentiates the “AC” pulse in conjunction with resistor R4.  Resistor R3 and transistors Q1 and Q2 provide transient/reverse polarity protection; the two transistors normally do not conduct.  Capacitor C5 (feedback capacitor, bridging the output and inverting input) is the characteristic feature of a charge-sensitive preamplifier and converts the pulse current to a voltage as it accumulates charge (integrates); note its tiny value (1 pF).  Decay time of the pulse is given by R4 * C5 = 100 Mohm * 1 pF = 100 μs, producing a distinctively long pulse tail.  Small signal gain of the circuit is referred to as "charge gain" and is given by 1/C5 = 1 V/pC.  Resistor R4 also provides a path for DC (FET leakage) current and establishes a DC operating point for the amplifier.  Amplification and inversion of the differentiated input pulse is provided by PNP transistor Q4.  The base of the transistor is biased at about 4.4 V using resistive divider R6-R7, and so the Q4 emitter (and Q3 drain) needs to be in the vicinity of 5.0 V for the transistor to remain in the “on” state continually (and conducting ~150 μA).  The Q4 emitter voltage is set by varying variable resistor VR1 such that the current sink formed by it and JFET Q3 provides an appropriate voltage drop (around 10 V) across resistor R5; this requires that Q3 conduct about 3.7 mA between drain and source.  Adjustment of VR1 also affects output DC bias.  A critical feature of the JFET is that it has an extremely high input impedance, and, since only minimal leakage current flows through its gate, it does not contribute significant current to the pulse and thus provides a useful interface with the amplification circuit; the high input impedance is maintained by keeping the gate-drain voltage low (~5 V) and temperature < 25°C (and stable).  Transistors Q5 and Q6 are arranged as a Darlington pair, and their purpose is to provide sufficient current (~3.9 mA) for operation of the 6.2 V/500 mW Zener diode, D1, used for biasing.  They also provide a small amount of current (microamps) to the noninverting input of the AD817 buffering op amp.

The high-impedance signal output by the differentiation and amplification circuit cannot drive the low-impedance, high capacitance cable to the main amplifier, and so a high-speed op amp – in this case, the AD817 (datasheet attached) – is used as a buffer and cable driver.  The op amp has an open-loop output impedance of 8 ohms, and so output impedance is set at 51 ohms by resistor R12.  Guaranteed output current is 50 mA, though this is far greater than necessary.  Further, the AD817 can drive an “unlimited” capacitive load (such as a length of cable) and has a guaranteed slew rate of 300 V/μs, unity gain bandwidth of 45 MHz, and 45 ns settling time to 0.1% (10 V step).  Op amps of this nature are typically used in video applications and are characterized not only by high speed but also by low input voltage noise.  Aside from being power-hungry, a general drawback of high-speed op amps is that the input bias current is enormous (3.3 microamps typical at 25°C for the AD817), and so input resistance is actually quite low – ~300 kohm in this case.  Compared to others in its class, the op amp requires relatively little quiescent current (7.5 mA guaranteed compared to 6.3 mA for the AD847 and 18 mA for the AD811), and this ensures that relatively little heat is generated within the box.  In its quiescent state, the AD817 dissipates no more than 225 mW.  Transistor Q6 dissipates about 60 mW while conducting ~4 mA, and transistor Q3 dissipates about 15 mW while conducting a similar current.  Transistors R5 and R10 dissipate ~40 mW and ~30 mW, respectively, and diode D1 dissipates about 25 mW.  I would guess that air temperature inside the box is slightly higher than room temperature (by 1 or 2°C), but the circuit is always running and presumably at thermal equilibrium locally – obviously, it’s warmest near the op amp.  In the vicinity of 25°C, the gate leakage current of JFET Q3 roughly doubles for every 10°C increase in temperature.

EDIT:  Regarding the paragraph below, a sine function was not a good choice for use in the simulator.  The small signal voltage gain of the circuit is inversely proportional to the capacitance of the feedback capacitor, C5.  If the capacitance is doubled, the gain decreases roughly by a factor of two.  For the JEOL circuit, the "charge gain" would be stated as 1/C5 = 1 V/pC.  The total gain of the circuit depends as well on detector capacitance and the capacitance of C3 (2.2 nF). 

In the simulator, when feeding the input a 100 Hz sine function, V(t), with 1 mV amplitude, I see a small signal voltage gain of about 135 at the output relative to the input (see plot below).  The phase is shifted by ~π/2 and is inverted relative to the input such that, if the input is a sine function, then the output is the negative cosine; this indicates that the output represents the negative of the first derivative (with respect to time) of the input (compare with figure 8.3 from Reed, 2nd ed., p. 93, below).  The AC output voltage (in the absence of C5) is given by V_out = -C3 * R4 * dV_in/dt = -0.22 s * dV_in/dt; i.e., the AC output voltage depends on frequency of the sine function or on dV/dt at the leading edge of a pulse from the X-ray counter anode wire; the negative sign is due to inversion of the signal by transistor Q4 (PNP).  Regarding the correction that I made to the figure from Reed, note that X-ray counter signal dV/dt initially is sharply negative, and so the signal is clearly inverted as well as differentiated to produce the output shown.  Also, Reed's Figure 8.2 (not shown) is in error, as it is missing the feedback resistor required for differentiation discharge of the feedback capacitor.

Figure 8.3 from Reed, “Electron Microprobe Analysis,” second edition:

EDIT:  Reed’s two drawings show only the process of inversion and not differentiation.  The tail on the amplified pulse is due to discharge of the feedback capacitor through the feedback resistor.  This resistor is missing from Reed's Figure 8.2.



Simulator input and output:

EDIT:  Ignore the plot below.



The following circuit (figure below) is equivalent functionally to the JEOL pre-amplifier, but, obviously, it is much simpler to interpret.  Substitution of this circuit is made possible because the gain of the circuit is not set by the amplifier (constructed either from an op amp or from discrete components) but rather is set by external components, as can be seen above in the expression for V_out.  As above, if the input is a sine function, then the output is the negative cosine (and negative sine is present at the inverting input of the op amp).  Disconnecting R4 produces cosine at the inverting input and negative sine at the output (with enormous gain).  If R4 is reconnected and C5 disconnected, the output may oscillate.

[Probeman]

Very nice work.  So where do you think the possible components making up what we call "dead time" are coming from? 

The gas detector itself?  And is bias voltage a factor?
The pre-amplifier circuit?
The amplifer/digitizer?  And is gain a factor?
The capacitance of the wires connecting them together!?   

All of the above?  What is their relative contribution towards what we measure, when we actually measure dead time?

SEM Geologist said he looked at the output of the Cameca detector or preamplifier (I can't find his specific post so not sure which), but I seem remember he said that the output pulses at that point were very short, much less than the dead times typically we measure. 

Is that what you see also on your JEOL instrument?

[Brian Joy]

Very nice work.  So where do you think the possible components making up what we call "dead time" are coming from? 

The gas detector itself?  And is bias voltage a factor?
The pre-amplifier circuit?
The amplifer/digitizer?  And is gain a factor?
The capacitance of the wires connecting them together!?   

All of the above?  What is their relative contribution towards what we measure, when we actually measure dead time?

SEM Geologist said he looked at the output of the Cameca detector or preamplifier (I can't find his specific post so not sure which), but I seem remember he said that the output pulses at that point were very short, much less than the dead times typically we measure. 

Is that what you see also on your JEOL instrument?

I don’t have answers to these questions yet, as I need to see how the signal is processed on the main amplifier board.  I’ve been getting hammered with work, so I probably won’t get to this for a while.  I’d like to hook up my oscilloscope to the preamplifier, but I don’t like the fact that the circuit common binding post is immediately adjacent to the binding posts for the +/-15 V supplies.  The op amp likely would survive a short circuit, but the transistors probably would not.

[sem-geologist]

First of all....
Just Wow!!! Brian, what a remarkable work had You done there!

I’ve attached datasheets for the Amptek A203 and also for the A250.  From the photo on the A203 (and 206) datasheet, it appears that the can contains a mini-circuit board with relatively few (surface-mount) components; it is likely a very simple circuit, but the datasheet provides only minimal information on its design.  Figure 8 from the datasheet for the presumably similar A250 provides a little more detail, but nothing is given on construction of the amplifier (still just an empty triangle).  I don't understand the need for the push-pull transistors at the output of the CAMECA circuit, as the AD847 should be able to drive the cable directly.

Cameca uses only A203 (that is charge sensitive preamplifier + shapping aplifier in a single package). A250 is not used and is not pin compatable with A203 and most important it (A205) is only a charge sensitive preamplifier (without Shapping amplifier part), also it is from next generation than A203 (designed a decade later). Encasing these small surface mount components in shielded capsule is not stupid at all - that can reduce the noise (especially EM) significantly. Especially on Cameca Spectrometer where HV bias generator is only ten centimeters away mounted very nearby. More detailed general schematics how charge sensitive preamplifiers works (internally) can be found at Cremat inc pages (other vendor making Preamplifier and shapping amplifier integrated chips), but I see You had sorted it out by reverse engineering Jeol circuit - Very Cool!!!.

Push-pull transistors after the 2nd differentiator on Cameca spectrometer clearly makes a class AB amplification stage (the current amplification) where AD847 gives only voltage amplification. And no - AD847 can't drive coaxial cable at its full achievable peak-to-peak range. My kind advice: documentation of components often contains misleading buzzwords at front pages (i.e. "unlimited", "ultra", "super", "extra", "unprecedented"...) and countless times I had learned in the hard way that best is just skip the front page and go straight into tables and charts. Here in documentation of AD847 https://www.analog.com/media/en/technical-documentation/data-sheets/AD847.pdf, look at Figure 3 (actually there are other figures which hints similar outcomes) in that and see that for Coaxial cable (which is 75 ohm terminated) it will be far from able to drive with full amplitude, and so if AD847 would drive it directly, there would be a huge pulse amplitude distortion and drop and that effect would float depending also from pulse density (from the count rate). There is a confusing and complicated part about OPAMP output impedance, ability to drive capacitive loads and its ability to drive cables, but fortunately Cameca engineers were very thoughtful and had not skipped that very important (and crucial at higher count rates) piece of hardware in design. Well it kind of could drive cable but probably p-p amplitude should not be more than 3V.

The JEOL WDS charge-sensitive preamplifier is constructed from discrete through-hole components (thank god)

And so does the Cameca too. Sure A203 hides the details... yeah but so does the all OPAMPS which are/ or just happens to be a huge bunch of tiny discrete components interconnected to expose such functionality in a single package. A203 sure probably is expensive, but I am pretty sure some custom mini board with i.e. Cremat inc CSP and SA could be made and mounted instead of that and without any re-soldering (as it use socket).

aside from capacitors, the component count is low.

System should be as simple as possible... but not oversimplified. Cameca electronics looks more overbuilt than JEOL - but every component there has its function. I remember  my first impression when I saw it first time was that Cameca circuits (all of them) are so much over-engineered, until I had not started digging into its functioning and after numerous self-repairs I am now convinced that actually it is absolutely surprisingly minimalistic, while still providing the means to control the stability. i.e. I see no circuit for bias control and regulation on this Jeol CSP board. Probably it is external on JEOL in other box with HV bias generator. Part above the A203 (not well exposed in my photos), are for setting and providing measured feedback of bias.

I need some time to digest the present circuit, but I already see 2 severe shortcoming in Jeol design which will introduce additional PHA shift: 1) lack of higher capacity capacitors for HV (look that yellow beefy cap on Cameca figure) - without it the higher count rate burst will be able to pull the bias voltage of detector wire down and thus diminish the gas amplification; 2) the lack of class AB signal amplification stage: high count rate will pull the amplitude of pulses down. No, the AD817 is not capable to drive properly terminated coaxial cables and preserve the full p-p range - same as AD847. Luckily such missing part could be easily added (I think) and should improve this at least there.(crossed-out: I was mislead to believe this board does more than only CPS,  the output of CPS does not need class AB amplification as AD817 wont need to produce large peak-to-peak patterns, but only very small voltage ramps and thus can do that directly through cable.)

 

[sem-geologist]

Some additional thoughts on differences on JEOL DIY and AMPTEK 203 design.

The following circuit (figure below) is equivalent functionally to the JEOL pre-amplifier, but, obviously, it is much simpler to interpret.  Substitution of this circuit is made possible because the gain of the circuit is not set by the amplifier (constructed either from an op amp or from discrete components) but rather is set by external components, as can be seen above in the expression for V_out.  As above, if the input is a sine function, then the output is the negative cosine (and negative sine is present at the inverting input of the op amp).  Disconnecting R4 produces cosine at the inverting input and negative sine at the output (with enormous gain).  If R4 is reconnected and C5 disconnected, the output may oscillate.

Yes, Your last figure (simplified schematics) summed it up very nicely and exactly - that is charge sensitive preamplifier for WDS. EDS charge sensitive preamplifiers are very similar, but they have no R4 (instead they have circuit which connects both sides of C5 capacitor to discharge it periodically). As You mentioned there is mistake in Reed's figure 8.2, but it is not so much important actually, it is rather not an error but just omission of details. Your simulation is a bit out of scope for this circuit and reveals processes which this circuit is not made for, and your simulation miss some crucial points. R4 function is not for differentiation (albeit as You had demonstrated here it does that for this type (100Hz) of input signal). R4 function is to discharge the building-up difference across the capacitor C5 and compensate the leakage current of FET. In Your simulation R4 has no opportunity to do that function as input signal (sine wave) for this simulation is symmetric around 0V and resets the difference across R4 on its own.  Also chosen extremely low frequency (100Hz) hides the integration part in output by few order of magnitude stronger differentiation part. The cap C5 blocks this kind of low freq signal, and thus Feedback of OPAMP is mainly through R4 resistor.

So to improve the simulation: 1) shift the input signal to negative Voltage so there would be only 0V-> -2mV -> 0V sine without any positive part (that would be more close to what is produced on detector wire). It would be even better to make pulsed input simulation (I am not sure if LTSpice alows that) with input pulse lenght of 5-10ns. 2) else increase the frequency significantly so that the capacitant parts of circuit would start to work in simulation which now are completely overshadowed by this type of low freq sinput ignal (something in 1MHz vicinity should work). You should see then more of integration and considerable decrease in differentiation. As far as I saw these details I am convinced that this JEOL Box is only the CPS part without any shapping (intentional differentiation of signal). So basically its function is like A250. Or half of A203 (only CPS part). I expect Oscilloscope will see no pulses at output from that box, but rather only cascades with decaying background in between.

Hey, but then I look to this again:

aside from capacitors, the component count is low.

Then actually Cameca part has less components, not more! the equivalent of this JEOL CSP is exactly half of A203 chip. So not a single component, but jus a half  . Also contrary to my first comment, actually this don't need class AB amplifier in this JEOL CSP, as there is not going to be huge peak-to-peak diferences (pulses), and only integrated cascades like on EDS (with difference to EDS, the background decaying between ramps due to R4, and not increasing by FET leakage current). Cameca preamplifier electronics looks more complicated (more components) - but it contains much more functions: HV bias set and control (as HV generator module is mounted on the same PCB), 2 stages of signal differentiations (pulse shapping) and class AB amplifier (as output has huge peak-to-peak amplitudes). Also there is lots of filtering of supply - that is generally present on every Cameca board, I would say roughly that ~25% of electronics in whole EPMA is supply stabilisation, filtering and conditioning, and preamplifier PCB is not an exception.

[Brian Joy]

Some additional thoughts on differences on JEOL DIY and AMPTEK 203 design.

Yes, Your last figure (simplified schematics) summed it up very nicely and exactly - that is charge sensitive preamplifier for WDS. EDS charge sensitive preamplifiers are very similar, but they have no R4 (instead they have circuit which connects both sides of C5 capacitor to discharge it periodically). As You mentioned there is mistake in Reed's figure 8.2, but it is not so much important actually, it is rather not an error but just omission of details. Your simulation is a bit out of scope for this circuit and reveals processes which this circuit is not made for, and your simulation miss some crucial points. R4 function is not for differentiation (albeit as You had demonstrated here it does that for this type (100Hz) of input signal). R4 function is to discharge the building-up difference across the capacitor C5 and compensate the leakage current of FET. In Your simulation R4 has no opportunity to do that function as input signal (sine wave) for this simulation is symmetric around 0V and resets the difference across R4 on its own.  Also chosen extremely low frequency (100Hz) hides the integration part in output by few order of magnitude stronger differentiation part. The cap C5 blocks this kind of low freq signal, and thus Feedback of OPAMP is mainly through R4 resistor.

So to improve the simulation: 1) shift the input signal to negative Voltage so there would be only 0V-> -2mV -> 0V sine without any positive part (that would be more close to what is produced on detector wire). It would be even better to make pulsed input simulation (I am not sure if LTSpice alows that) with input pulse lenght of 5-10ns. 2) else increase the frequency significantly so that the capacitant parts of circuit would start to work in simulation which now are completely overshadowed by this type of low freq sinput ignal (something in 1MHz vicinity should work). You should see then more of integration and considerable decrease in differentiation. As far as I saw these details I am convinced that this JEOL Box is only the CPS part without any shapping (intentional differentiation of signal). So basically its function is like A250. Or half of A203 (only CPS part). I expect Oscilloscope will see no pulses at output from that box, but rather only cascades with decaying background in between.

Hey, but then I look to this again:

aside from capacitors, the component count is low.

Then actually Cameca part has less components, not more! the equivalent of this JEOL CSP is exactly half of A203 chip. So not a single component, but jus a half  . Also contrary to my first comment, actually this don't need class AB amplifier in this JEOL CSP, as there is not going to be huge peak-to-peak diferences (pulses), and only integrated cascades like on EDS (with difference to EDS, the background decaying between ramps due to R4, and not increasing by FET leakage current). Cameca preamplifier electronics looks more complicated (more components) - but it contains much more functions: HV bias set and control (as HV generator module is mounted on the same PCB), 2 stages of signal differentiations (pulse shapping) and class AB amplifier (as output has huge peak-to-peak amplitudes). Also there is lots of filtering of supply - that is generally present on every Cameca board, I would say roughly that ~25% of electronics in whole EPMA is supply stabilisation, filtering and conditioning, and preamplifier PCB is not an exception.

I chose a sine wave in the simulation simply because it was convenient.  I was unable to get a square wave (with defined rise time) to work, though I might try again.  It’s possible/likely that I’ve misinterpreted some aspects of operation of the circuit, and this is why I need to examine how the signal is processed on the main amplifier and shaper board.  When I look at the topology of the simplified circuit that I drew, I see a differentiator with a stabilizing feedback capacitor, but I haven’t considered the effects of varying dV/dt carefully enough.

Yes, I see your point now about Figure 3 in the AD847 documentation.  The JEOL preamplifier circuit output does not swing anywhere close to the supply rails, though, and so the AD817 can drive the cable directly.  The transistors and diodes at the output of the Cameca circuit make sense to me now, as I’d forgotten that the Cameca circuit output has much greater amplitude.

The reason I mentioned the A250 is that, like you stated, it does the work of the A203 without the A206 and likely performs a similar function as the JEOL preamplifier.  I can’t imagine that the A250 differs topologically at all from the A203; perhaps the amplifier has been improved somehow, but no details are given.  If you look at the last page of the datasheet for the A203, note that the output from pin 13 (charge amplifier output) of the A203 when fed the trailing edge of a square wave is a positive pulse with short rise time and long tail.  Does this not represent inversion and differentiation with tail length controlled by the feedback resistor and feedback capacitor?  See also figure 1 of the attached application note for the A250.  The amplifier itself will have only minimal effect on the shape of the output as long as its slew rate is adequate.

[Brian Joy]

I forgot that I hadn’t tried running the simplified circuit simulation with square wave input.  The simulator is “touchy” and often refuses to converge as the component count rises.  I needed to switch to a faster op amp, the AD744, which has a typical slew rate (unity gain) of 75 V/μs and input impedance of 3 TΩ (input bias current = 30 pA at 25°C).  Using the square wave input, I created a single 200 μV negative step with rise/fall time set at 10 ns.  Here is the simplified circuit with modifications to the input:



Here is what the input square wave looks like (noting that the step is not perfectly vertical):



Here is the signal at the inverting input of the op amp:



Finally, here is the output:

[Brian Joy]

I finally got the simulated JEOL WDS preamplifier circuit to work with square wave input.  I simply discarded the buffer amplifier and all components associated with it.  Even just using the economical but low noise 2N5087 as the voltage amplifying transistor Q4, the slew rate (dV/dt) of the amplifier formed by it and the JFET, Q3, which provides high input impedance to protect the signal passed to Q4, is comparable or superior to that of a high-speed, low-noise, high impedance-input op amp like the ADA4637, which gives much better performance than the AD744.  Rise time of the output pulse must be minimized, and so the amplifier must be very fast.  Here is the output of the circuit when I feed it the leading edge of an inverted square wave with -200 μV amplitude and 5 ns rise time:



The capacitance of C5 is tiny (1 pF), and the resistance of R4 is huge (100 MΩ).  Values of C5 and R4 must fall within narrow ranges in order to produce a pulse of appropriate shape (with steep leading edge) such that it may be modified further by the shaping amplifier.  By varying the component values within reasonable limits (C5 = 0.5-5 pF, R4 = 50-500 MΩ), the tail can be made to change shape drastically; small signal voltage gain is also affected.  It’s instructive to vary the value of R4 while keeping C5 constant and vice versa and then watch how the output changes.  Decreasing the value of one or the other may eventually cause "ringing" and circuit failure.  Replacing Q4 with a power transistor with large collector capacitance (C_cb), such as the D45H11, will also change the output dramatically:



I’ve attached the .asc file that can simply be opened in LTSpice and run (by clicking on the running man).  When it is run in AC mode (specified by the line on the schematic containing “.tran”), a new window will open.  Hovering over the output wire of the schematic will produce a voltage probe symbol, and clicking on this will cause the output voltage as a function of time to appear in the new window.  Resistor and capacitor values can be changed by right-clicking on them in the schematic.  Right-clicking on a transistor when the pointing finger appears will allow the transistor to be switched with another.

Obviously, considering the long tail of the output pulse from the preamplifier, subsequent X-ray counts may produce pulses superimposed on the tail(s) of (a) previous one(s).  In the following figure from the Cremat website (https://www.cremat.com/why-use-csps/), this situation is shown in the lower (channel 1) oscilloscope trace prior to processing by the shaping amplifier (upper trace, channel 2).  Not only does the shaping amplifier separate and shape the pulses, it also improves the signal-to-noise ratio dramatically.

[sem-geologist]

The AD744 is not so terribly bad for simulation. As You had noticed replacing it with something else changes the output extremely. Still the problem of simulation is not the U1 or Q4 but the signal You are letting into which is far away from realistic. the Preamplifier is intended to integrate (that is why it is called a "charge sensitive") and not discriminate - discrimination is a side effect on this (WDS) type of preamplifier due to R4. There is few problems with square wave (with long period) being fed is that it behind has many Sine waves with different frequencies (look for Gibb's effect). And this resistor R4 sees all those Sine waves with long period and overshadows the tiny integrated signal with huge differentiation. Another problem is that Your integration part can't be simulated as this capacitor is tiny (1pF) and gets fully saturated with this kind of very long lasting -0.2mV negative square wave part (integration hits the capacity of 1pF capacitor as whole 5ms of that negative voltage needs to be integrated).

So we should ask: What are more close-to-reality values for pulse-rise, pulse-on and pulse-fall times so that simulation would produce closer to the real world result? I find it quite controversial subject. Wish I could measure that also on our machines (albeit it would help a little, as You will see further), I however have no oscilloscope or probes for directly measuring such  high HV signals. I had an attempt trying measuring it before on the preamplifier input pin which is after coupling capacitor, but result was very mixed (it is very hard to measure it correctly there and I could not get peak over noise). Your chosen value for pulse-on is 5ms - and that looks for me more like few orders of magnitude too long, more something from a book of Geiger–Müller tube (where is avalanche consuming whole wire). With very localized Townsend avalanche (typical for proportional regime) the electron ring-collapse on anode should be much more short-lived event than that - Easily at least thousand times shorter (<5µs). Collapsing electrons on the anode produces voltage drop, However, restoration to voltage before it needs time which is defined by anode and coupling capacitor capacitance the resistor between anode and HV generator. With naive approach calculating the RC time constant I get this tau = 0.0022 µF * 100Mohm = 0.22s ! and full restore of voltage in anode would require 5 x tau = 1.1 s ! But in real world for sure we don't have that kind of situation, as we would be able to drain out the bias of anode near instantly during any even low count rate counting. Maybe this equation "τ=RC" using the full capacity of capacitor and anode is completely not applicable here as the capacitor (and anode) is "near full" positively charge (at set voltage). Should time needed for bias restoration work rather with some fF (femto) capacities?

And then I found this nice experimental stuff:
https://physicsopenlab.org/2017/07/23/x-ray-proportional-counter-2/
and as You will see it is much more close what we are told in some books and what we expect logically from the Proportional counters and its ability to go up and above 1Mcps (our experienced limitations are in signal handling).

By those measured examples it is clear that whole event (at least for that kind of proportional counter used in experiment) should take only 200ns !
So If we set the input pulse model like this: rise_time = 75ns, time_on = 25ns, fall_time= 100ns we get this with single pulse:

blue at top - output of OPAMP, green at bottom - input signal (abstracted GPC signal).

and when zoomed out:


Please notice the following undershot. That is as AD744 OPAMP is not most perfect OPAMP for this kind of work. This is called balistic deficit. With keeping same OPAMP we can get rid of that by increasing resistance of feedback resistor. There is many reasons (including this) why no one use ready cheap COTS OPAMPS for charge sensitive preamplifiers and either uses specialised CHIPS (Creamat, AMPTEK) or make it from a scratch (JEOL).

I find LTSpice to be nice simulation tool.We can define train of pulses. I.e. this simulation can be extended further by asking to repeat pulses every 2µs (period 2µs). This how it would look for 50 pulses every 2µs (zoomed-in version):


and then zoomed out version which again reveals trouble with "ballistic deficit":


but is it a trouble or a feature? It depends how we would look to that: It could be a feature (the same as bipolar pulses which prevents overlaps from saturating the supply voltage) and in this case it is the same. So interestingly this demonstrates that even this AD744 could be used for preamplification. At least theoretically....

[Brian Joy]

The AD744 is not so terribly bad for simulation. As You had noticed replacing it with something else changes the output extremely. Still the problem of simulation is not the U1 or Q4 but the signal You are letting into which is far away from realistic. the Preamplifier is intended to integrate (that is why it is called a "charge sensitive") and not discriminate - discrimination is a side effect on this (WDS) type of preamplifier due to R4. There is few problems with square wave (with long period) being fed is that it behind has many Sine waves with different frequencies (look for Gibb's effect). And this resistor R4 sees all those Sine waves with long period and overshadows the tiny integrated signal with huge differentiation. Another problem is that Your integration part can't be simulated as this capacitor is tiny (1pF) and gets fully saturated with this kind of very long lasting -0.2mV negative square wave part (integration hits the capacity of 1pF capacitor as whole 5ms of that negative voltage needs to be integrated).

I am only trying to simulate a single pulse at this point.  The -0.2 mV square wave that I set up has a rise time of 5 ns, and the circuit responds only to the leading edge during the simulation time (0.7 ms).  Capacitor C5 will not saturate because C3 only allows current to pass at the leading edge of the pulse.  You can verify this by checking the output while varying the value of C5.

I have set up the square wave in a manner that is consistent with the testing instructions in the first paragraphs of the A250 application note that I attached earlier.  For simulation of a single pulse, the "on" time of the square wave is irrelevant, and so I set it arbitrarily at 5 ms.  I may not have set the amplitude properly, but this will not change the shape of the output pulse.

[sem-geologist]

I am only trying to simulate a single pulse at this point.  The -0.2 mV square wave that I set up has a rise time of 5 ns, and the circuit responds only to the leading edge during the simulation time (0.7 ms).  Capacitor C5 will not saturate because C3 only allows current to pass at the leading edge of the pulse.  You can verify this by checking the output while varying the value of C5.

I have set up the square wave in a manner that is consistent with the testing instructions in the first paragraphs of the A250 application note that I attached earlier.  For simulation of a single pulse, the "on" time of the square wave is irrelevant, and so I set it arbitrarily at 5 ms.  I may not have set the amplitude properly, but this will not change the shape of the output pulse.

ok, maybe C5 won't saturate, but C3 does not pass only leading edge but whole pulse - that is not obvious due to voltage rasing at opamp side of C3 - due to the feedback of OPAMP.

application note in A250 for single edge is only for testig purpoises - to test that circuit works (at all) - to get such edge signal it is enought to have a switch signal to ground. Contrary - such real-life 200ns pulse for testing would require fancy signal generator (or physical detector). The total time ("fall"+"on"+"rise") is not irrelevant - but the most relevant for pulse shape. Look and compare for how long time your simulated output edge takes, and mine.

[Brian Joy]

application note in A250 for single edge is only for testig purpoises - to test that circuit works (at all) - to get such edge signal it is enought to have a switch signal to ground. Contrary - such real-life 200ns pulse for testing would require fancy signal generator (or physical detector). The total time ("fall"+"on"+"rise") is not irrelevant - but the most relevant for pulse shape. Look and compare for how long time your simulated output edge takes, and mine.

But should your output pulse actually be so narrow?  It also shows signs of instability.  In the oscilloscope traces from the Cremat website that I posted above, note that the time division is 40 μs.  In that particular case, the charge amplifier has Rf = 100 MΩ and Cf = 1.4 pF, giving a time constant of 140 μs and producing a tail that is visible for > 240 μs.  This is similar to my output from the JEOL circuit when using square wave input.  Your input pulse is so narrow that it appears to be discharging C5 before R4 has a chance to do so.  For instance, if, using your input pulse, I increase the value of C5 to 3 pF (in the JEOL circuit), the output is stabilized, but the length of the tail barely changes (though the C5*R4 time constant is 300 μs).  The small signal voltage gain is also very low.

As I’ve worked with the simulated JEOL circuit, I’ve had a hard time characterizing small signal voltage gain, but now I see the pattern.  Given the value of C5 (1 pF), as R4 decreases below a value somewhere in the tens MΩ, the gain will start to decrease such that the behavior of the circuit becomes more like that of a transimpedance amplifier than a charge amplifier; I had confused both topologically with a differentiator.  If R4 = 100 kΩ, for instance, the circuit should behave essentially purely as a transimpedance amplifier stabilized by C5 (as the output may otherwise oscillate, as it does anyway in the simulator).  When R4 attains a large enough value, though, C5 will remain charged for a long enough period such that the gain will vary inversely with C5 and will be insensitive to variation in R4.  For instance, if R4 = 100 MΩ and if C5 is increased from 1 pF to 3 pF, then the output amplitude will fall by a factor of very roughly three; I obtain very similar results for R4 = 300 MΩ.  I need to think about this some more, but I believe I've cleared up the sources of my confusion in distinguishing a charge-sensitive amplifier from a transimpedance amplifier or differentiator stabilized by a feedback capacitor.  I see now that the first two may be AC- or DC-coupled.

[Brian Joy]

For Jeol I am not so pretty sure, as IMHO their preamplifier miss some important and crucial higher capacity HV backup capacitor and because of that bias voltage of cathode could be significantly drained down at burst of high rate X-ray (similarly to G-M counter).

Can you explain what you mean by “higher capacity backup capacitor”?  The large yellow capacitor that you show in the photo of the A203 preamplifier/shaper is a 220 nF metallized polypropylene film capacitor (low dielectric absorption, as with ceramic).  This couldn’t possibly be a coupling capacitor, though, as it would change the pulse shape and gain tremendously – it would saturate the output.  A mica(?) capacitor is located immediately adjacent to the A203.  What is its purpose?  Could you post a schematic of the CAMECA circuit (with the A203 as a “black box”)?  You’ve also stated that the AD847 differentiates the signal to produce bipolar output.  I only see two ceramic capacitors next to the op amp, presumably for filtering of the +/- DC supplies.  I am lost without a schematic (and also sometimes with one).

[sem-geologist]

Can you explain what you mean by “higher capacity backup capacitor”?  The large yellow capacitor that you show in the photo of the A203 preamplifier/shaper is a 220 nF metallized polypropylene film capacitor (low dielectric absorption, as with ceramic).  This couldn’t possibly be a coupling capacitor, though, as it would change the pulse shape and gain tremendously – it would saturate the output.

Yes exactly that yellow self healing film capacitor. Its purpose is similar to capacitor C1 in your Schematics - it is called bypass capacitor (C2 is also bypass capacitor) - its purpose is to store reserve charge then it is not needed, and give away then there is a demand. Without C1 and C2 the bias (or with too low values) voltage in wire would drop below potential needed to make Townsend avalanches after enough of electrons from avalanches would reach the wire - basically detector would be blind for some fraction of time as it would require substantial time to equalize voltage back across R1 and R2 (restore the bias voltage on the wire after town send avalanches). So there is huge difference on charge reserve presented on Cameca instruments and that Jeol Preamplifier box: both C1 and C2 is only 2.2nF on Jeol. C2 is 10nF (!) and C1 is 220nF on Cameca (R1 is twice larger too), and I want to emphasize here - that much bigger capacity of reserve is despite HV supply sitting much closer than on Jeol - just ~10cm away. How far away the HV supply is situated (length of cable) on Jeol Probe? IMO C1 of only 2.2nF makes no sense - or makes sense only from space constraints - so it could fit into the box.

A mica(?) capacitor is located immediately adjacent to the A203. What is its purpose?

How had You knew it is mica? (I don't know ).
First of all A203 datasheet requires that output would be decoupled, and thus it is its first purpose. Its other function is being part of differentiation by AD847.
 

You’ve also stated that the AD847 differentiates the signal to produce bipolar output.  I only see two ceramic capacitors next to the op amp, presumably for filtering of the +/- DC supplies.

Yes those two small capacitors are by-pass caps. The capacitor for differentiation is that "Mica" capacitor You mentioned above.

Could you post a schematic of the CAMECA circuit (with the A203 as a “black box”)?
....
 I am lost without a schematic (and also sometimes with one).

I would love to share schematics, but LEGALLY I can only share only my own reverse engineered (from physical hardware) schematics, which I can see from physical PCB and probing the connections between components. All Cameca original schematics are marked with "This Document Is Property of CAMECA; it cant be reproduced or/and transmitted without authorization" - That is the major pain. Unfortunately some of traces runs on the other side of PCB, and needs either dismantling the PCB or using some resistance probing technique to make the Schematics from a scratch. I will share when I will have some.

[Brian Joy]

Can you explain what you mean by “higher capacity backup capacitor”?  The large yellow capacitor that you show in the photo of the A203 preamplifier/shaper is a 220 nF metallized polypropylene film capacitor (low dielectric absorption, as with ceramic).  This couldn’t possibly be a coupling capacitor, though, as it would change the pulse shape and gain tremendously – it would saturate the output.

Yes exactly that yellow self healing film capacitor. Its purpose is similar to capacitor C1 in your Schematics - it is called bypass capacitor (C2 is also bypass capacitor) - its purpose is to store reserve charge then it is not needed, and give away then there is a demand. Without C1 and C2 the bias (or with too low values) voltage in wire would drop below potential needed to make Townsend avalanches after enough of electrons from avalanches would reach the wire - basically detector would be blind for some fraction of time as it would require substantial time to equalize voltage back across R1 and R2 (restore the bias voltage on the wire after town send avalanches). So there is huge difference on charge reserve presented on Cameca instruments and that Jeol Preamplifier box: both C1 and C2 is only 2.2nF on Jeol. C2 is 10nF (!) and C1 is 220nF on Cameca (R1 is twice larger too), and I want to emphasize here - that much bigger capacity of reserve is despite HV supply sitting much closer than on Jeol - just ~10cm away. How far away the HV supply is situated (length of cable) on Jeol Probe? IMO C1 of only 2.2nF makes no sense - or makes sense only from space constraints - so it could fit into the box.

A mica(?) capacitor is located immediately adjacent to the A203. What is its purpose?

How had You knew it is mica? (I don't know ).
First of all A203 datasheet requires that output would be decoupled, and thus it is its first purpose. Its other function is being part of differentiation by AD847.
 

You’ve also stated that the AD847 differentiates the signal to produce bipolar output.  I only see two ceramic capacitors next to the op amp, presumably for filtering of the +/- DC supplies.

Yes those two small capacitors are by-pass caps. The capacitor for differentiation is that "Mica" capacitor You mentioned above.

Could you post a schematic of the CAMECA circuit (with the A203 as a “black box”)?
....
 I am lost without a schematic (and also sometimes with one).

I would love to share schematics, but LEGALLY I can only share only my own reverse engineered (from physical hardware) schematics, which I can see from physical PCB and probing the connections between components. All Cameca original schematics are marked with "This Document Is Property of CAMECA; it cant be reproduced or/and transmitted without authorization" - That is the major pain. Unfortunately some of traces runs on the other side of PCB, and needs either dismantling the PCB or using some resistance probing technique to make the Schematics from a scratch. I will share when I will have some.

OK, thanks for the clarification.  Yes, I’m aware of the functions of reservoir/bypass capacitors, but I was thrown off by the especially large capacitance and also by the lack of ability to see the whole circuit.  Does 220 nF not strike you as overkill?  Certainly, JEOL could have fit 10 nF ceramic bypass capacitors in the small box, but a 2.2 nF capacitor can accommodate 13.7 billion electrons per volt (and keep in mind that a 1 pF feedback capacitor is sufficient in the preamplifier for a single pulse).

I don’t know that the capacitor next to the A203 is mica – maybe it’s just ceramic with a weird shape.  I can’t quite read the label on it.  I can see a trace from it that leads to the A203; for differentiation, the capacitor ought to be closer to the op amp.  Which capacitor is the coupling capacitor?  Is it the smaller blue ceramic capacitor next to the 220 nF film capacitor?

Although the pulse that you showed (repeated below) appears bipolar, I’m not convinced that the AD847 is serving as a differentiator.  This would also invert the signal and would provide a low impedance path around the op amp, which would defeat its purpose as a buffer (but maybe the feedback resistor would be large enough).  The depression after the pulse seems too pronounced to be due to undershoot from the shaper, though.  It also appears that the pole-zero cancellation network is in fact being used, as I can see a resistor with brown-black-black-yellow color bands leading toward pins 12 and 13.  Maybe I’ll just have to wait for your schematic.

Regarding the A203, the datasheet is frustrating, as it provides very little information on the circuit inside.  The feedback capacitor for the charge amplifier is 2 pF, but the fall time is stated as being only 30 μs.  If this represents the Cf * Rf time constant, then this would imply Rf = 15 MΩ, which is strangely small.  At 250 ns, the shaping time constant is also quite small.  I guess this would help prevent pulse pileup at the expense of signal-to-noise ratio.  Maybe someone could scavenge an A203 from a decommissioned SX-100 and pry the top off?  Wishful thinking.  I haven’t gotten to the JEOL shaping amplifier yet; the main amplifier board and power supplies are located in the “intelligent unit.”

EDIT:  I believe that differentiation occurs between the A203 and the AD847 buffer amplifier and involves the odd-shaped capacitor and probably the resistor next to it.  Like I noted above, I can see a trace from the capacitor that goes underneath the A203 (i.e., toward its output).  Also, one lead of the resistor oriented parallel to the capacitor is located very close to pin 3 (noninverting input) of the AD847.